There are different types of substrates for making radiofrequency (RF) devices at the present time.
A first type of substrate includes substrates comprising a silicon layer on an insulating substrate, for example such as Silicon on Quartz (SOQ), Silicon on Sapphire (SOS) or Silicon on Glass (SOG) substrates.
These substrates give excellent radiofrequency performances but have very poor characteristics concerning logical devices, due to the lower quality of the silicon. They are also very expensive.
A second type of substrate is a High Resistivity (HR) bulk Silicon substrate. High Resistivity Means Especially an Electrical Resistivity of More than 500 Ohm.cm.
Performances of these substrates are lower than the performances of the first substrates, and the logical devices do not benefit from the advantages of SOI type structures, although they do have the advantage of not being expensive.
A third type of substrate is a High Resistivity Silicon on Insulator (HR-SOI) substrate, in other words composed of a silicon layer on a high resistivity silicon substrate, a thick oxide layer being buried at the interface. This is why this oxide layer is usually referred to as BOX (Buried OXide).
Such substrates are particularly advantageous for the functioning of logical devices, but their radiofrequency performances are not as good as SOQ and SOS substrates.
These substrates have the disadvantage that they sometimes include a low resistivity layer under the oxide layer.
For the purposes of this text, a low resistivity, means electrical resistivity less than 500 Ohm.cm.
The presence of this low resistivity layer may be due to surface contamination of the substrates (for example due to condensation of boron and/or phosphorus) before bonding. These contaminants are then encapsulated at the bonding interface, and can diffuse into the high sensitivity substrate.
Another cause of the formation of the low resistivity layer occurs when the initial substrate is a silicon substrate with a high density of interstitial oxygen atoms; a heat treatment is then necessary to make the oxygen precipitate and obtain the required high resistivity. However, oxygen atoms can diffuse in the substrate before or during this treatment, which leads to the formation of regions in the substrate with a low precipitation rate—and therefore low resistivity—, particularly close to the surface of the substrate.
These two causes are difficult to control at the moment.
A fourth type of substrate consists of an HR-SOI type substrate in which the HR substrate is improved by the addition of traps.
Different techniques have been developed for this purpose but they have the disadvantage that they are very sensitive to heat treatments used to manufacture the SOI and then devices on the SOI.
Thus, a layer of polycrystalline silicon can be deposited between the oxide layer (BOX) and the HR substrate.
Further information on this subject can be found in publications written by D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., pp. 46-47, 2004; D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer and J.-P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate”, IEEE Transactions on Electron Devices, vol. 55, no. 7, pp. 1664-1671, 2008; and D. C. Kerr and al., “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”, 978-1-4244-1856-5/08, IEEE 2008 IEEE.
FIG. 1 shows such a substrate that comprises an HR silicon substrate 1, followed successively by a polycrystalline silicon layer 4, an oxide layer 2 and a monocrystalline silicon layer 3 that forms the active layer of the substrate.
However, the polycrystalline silicon recrystallizes at high temperature, and doping agents present at the interface between the polycrystalline silicon layer and the HR silicon substrate diffuse in the HR silicon substrate, which has the effect of reducing its resistivity.
Curve (a) in the graph in FIG. 2 (shown in dashed lines) illustrates the variation in the electrical resistivity ρ of substrate 1 in FIG. 1 covered by the polycrystalline silicon layer 4 as a function of the depth d after heat treatment at 1100° C. for 6 hours, simulating the thermal budget for production of the HR-SOI substrate.
Therefore, on this graph the abscissa d=0 corresponds to the upper surface of the polycrystalline silicon layer, in other words the interface between the BOX 2 and the polycrystalline silicon layer 4.
Resistivity is measured using the Spreading Resistance Profiling (SRP) method.
As can be seen on curve (a), the resistivity reduces very quickly in layer 4 to reach a minimum level that extends into substrate 1, beyond the interface between the polycrystalline silicon and the HR silicon.
Beyond a depth of the order of 2 μm under the BOX, the resistivity of the substrate 1 quickly increases to reach high resistivity values.
The drop in resistivity observed on this curve can be explained by recrystallization of polycrystalline silicon during the above-mentioned heat treatment and/or by diffusion of the doping agents at the interface between the layer 4 of polycrystalline silicon and the substrate 1, or even contamination of the upper surface of layer 4.
As can be seen in FIG. 5 in which photograph (a) is an image of the interface between layer 4 and substrate 1 taken by a transmission electron microscope (TEM), about one third of the polycrystalline silicon has recrystallized starting from the interface with the substrate 1.
Another technique consists of diffusing gold through the entire HR silicon substrate.
For example, information on this subject can be found in the paper written by D. M. Jordan, Kanad Mallik, R. J. Falster, P. R. Wilshaw, “Semi-insulating silicon for microwave devices”, Solid-state phenomena Vols 156-158 (2010) pp 101-106, in which the authors propose to introduce gold impurities into the silicon substrate by means of a gold deposit on the substrate followed by diffusion under the effect of a high temperature heat treatment. The effect of these gold impurities is to introduce deep levels in the forbidden band and block the Fermi level in the middle of the forbidden band, which generates a very high resistivity of the material.
However, it is essential to prevent gold from escaping from the substrate; gold is an element that very strongly shortens the life of silicon and contamination of the clean room and/or the thin silicon layer would seriously degrade the performances of devices manufactured in it.
Efficient diffusion barriers (for example nitride barriers) have to be provided to prevent gold from escaping, but this would be at the detriment of the performances of the devices. For example, nitride charges affect transistor threshold voltages.
Another relevant patent is U.S. Pat. No. 6,548,382 that on the contrary proposes to avoid the presence of impurities in the HR substrate by trapping them in a layer formed either by implantation of gaseous species or by implantation of particles that form precipitates insensitive to later heat treatments. The particles may consist of oxygen and/or other materials, excluding metals and semiconductors. These precipitates then form impurity trapping sites.
Document WO 2010/002515 discloses an alternative to the use of an HR silicon-based substrate in the HR-SOI substrates mentioned above, by replacing this bulk base substrate by a structure comprising a thick semiconducting layer with high resistivity on a support with standard resistivity.
To prevent the risk of doping agents or contaminants present in the support diffusing into this highly resistive semiconducting layer and thus reducing its resistivity, it is recommended that a diffusion barrier should be placed between the support and the semiconducting layer. Such a diffusion barrier may consist of one or several layers of silicon oxide and/or silicon nitride and has a thickness of at least 20 nm.
Moreover, this resistive layer can be considered like a substrate due to its high thickness (of the order of 50 to 100 μm).
Substrates for radiofrequency devices are affected by the electric field that, due to the high frequency, penetrates into the substrate and affects any charge carriers that it meets with the consequences firstly of useless energy consumption (called transmission loss), and secondly it can influence other devices whose behavior will be modified through the substrate (called the crosstalk phenomenon).
Moreover, increasing and decreasing the signal induces a variation in the capacitance of the substrate that causes the generation of waves at harmonic frequencies of the main frequency. These harmonic waves and combinations of them can form parasite signals particularly damaging for radiofrequency applications. The use of a polycrystalline silicon layer blocks the potential under the BOX, thus limiting capacitance variations and therefore reducing the power of the generated harmonic waves.
Finally, the presence of any charges in the BOX and the use of DC voltages by some devices can lead to the creation of an accumulation or inversion layer (therefore highly conducting) under the BOX. The polycrystalline silicon layer eliminates this negative effect by blocking the potential under the BOX.
Therefore, a first purpose of the invention is to define a method for manufacturing an HR-SOI type substrate with improved properties for radiofrequency applications.
Another purpose of the invention is to procure an HR-SOI type substrate in or on which components for radiofrequency devices with improved operating characteristics will be manufactured.